Course Module for Verilog

Title	Module	Lab
Overview of Digital Design With Verilog HDL	Typical Design Flow Importance of HDLs Popularity of Verilog HDL Trends in HDLs	Introduction to ModelSim Softwaree
Hierarchical Modeling Concepts	Design Methodologies Modules Instances Components of a Simulation	Installation Of ModelSim
Basic Concepts	Lexical Conventions Number Specification Strings Identifiers & Keywords Escaped Identifiers Data Types System Tasks & Compiler Directives Modules Ports Hierarchical Names	Basic Programs using ModelSim
Gate-Level Modeling	Gate Types Gate delays.	Examples Gate-level Multiplexer 4-Bit Ripple Carry Full Adder Gate Delays Rise, Fall & Turn-off Delays Rise Delay Fall Delay Turn-off Delay Min/Typ/Max Values Min Value Typ Val Max Value Delay Example
Dataflow Modeling	Continuous Assignments Delays Expressions, Operators & Operands Operator Types	Examples 4-to-1 Multiplexer Method 1: Logic Equation Method 2: Conditional Operator 4-bit Full Adder Method 1: Dataflow Operator Method 2: Full Adder With Carry Look-ahead Ripple Counter etc.
Behavioral Modeling	Enabling Layers. Structured Procedures Procedural Assignments Timing Controls Conditional Statements Multiway Branching Loops Sequential & Parallel Blocks	Examples 4-to-1 Multiplexer 4-bit Counter Traffic Signal Controller Specifications Verilog Description Stimulus
Task & Functions	Difference between Tasks & Functions Tasks Functions Automatic (Recursive) Functions Constant Functions Signed Functions	Programs on Examples Related to Concerned Topic
Advanced Verilog Topics Timing & Delays	Types Of Delay Models Path Delay Modeling Timing Checks Delay Back- Annotation	Programs onExamples Related to Concerned Topic
Logic Synthesis with Verilog HDL	Logic Synthesis & it’s impacts Verilog HDL Synthesis Synthesis Design Flow An Example of RTL-to-Gates Verification of the Gate-Level Netlist Modeling Tips for Logic Synthesis	Example of Circuit Synthesis on FPGA board (Spartan & Virtex Evaluation Boards)
Advanced Verification Techniques	Traditional Verification Flow Assertion Checking Formal Verification
Verilog Projects Using RTL Coding and Synthesis	Project Specification Analysis Understanding the architecture Module level implementation and verification Building the Top level module Implementing the design onto the FPGA board
Output Generation and Documentation	Creating a new Output Job file. Setting up Print job option. Setting up Print job options. Creating CAM files. Running the Output Generator. Drawing Requirements. Assembly Drawing. Master Drawing. Exercise – adding an Out Job file to the project.