VHDL

COURSE FOR Engineering Students / COLLEGE STUDENTS
Title Module Lab
Introduction to VLSI
  • VLSI Design Flow
  • ASIC Vs FPGA
  • RTL Design Methodologies
Introduction to VHDL
  • Why use VHDL ?
  • Shortcomings
  • Introduction to ModelSim Software/li>
Design Units
  • Entity
  • Architecture
  • Configuration
  • Package Body
  • Design Library
  • Installation Of ModelSim
Language Construct
  • Literals
  • Identifiers
  • Data objects
  • Data types
  • Data operators
  • Basic Programs using ModelSim
Design styles
  • Data flow description
  • Behavioral descriptions
  • Structural descriptions
  • Programs related to Examples on Different Design Styles
Concurrent and Sequential Elements
  • Concurrent statements
  • Sequential Statements
  • Delta Delay
  • Variable and memory
  • Shared variables
    Examples
  • Combinational Circuits
  • Sequential Circuits
  • Circuits with Delay
State Machines
  • Mealy machines
  • Moore Machines
  • Encoding Schemes
  • Program to implement the State Machine
Memory
  • Memory Prototype
  • Packages
  • Implementing a Memory Prototype
Functions and procedures
  • Functions
  • Procedures
  • Predefined Functions and Procedures
  • Programs Related on Conversion/Extracting Different Mathematical Values
File Operations
  • Write Operations
  • Read Operations
  • Writing Output onto a display device
  • Programs to Read/ Write the Output Values
UVM-Universal verification Methodology
  • Introduction to UVM Methodology
  • UVM TB Architecture
  • Stimulus modeling
  • Creating UVCs and Environment
  • UVM Simulation Phases
  • Testcase classes
  • Configuring TB Environment
  • UVM sequences
  • UVM Sequencers
  • Introduction to Register Modeling
VHDL Projects
  • Project Specification Analysis.
  • Understanding the architecture.
  • Module level implementation and verification.
  • Building the Top level module.
  • Implementing the design onto the FPGA board.